1. Field
Example embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, example embodiments relate to a semiconductor device including a transistor having a vertical channel region and a method of manufacturing the same.
2. Description of the Related Art
Generally, transistors included in semiconductor memory devices have a source region for supplying electrons or holes, a drain region for consuming those electrons or holes, and a gate electrode for controlling a flow of the electrons or the holes. A passing region of the electrons or holes from the source region to the drain region may be called a channel region. An insulation layer may be further provided in the transistor to electrically insulate the gate electrode and the channel region.
A gate structure of a conventional transistor may include a stacked structure of a gate insulation layer and a gate electrode. In addition, source and drain regions may be formed in portions of a substrate adjacent to both sides of the gate electrode. Such a transistor has a channel region formed along a horizontal direction to the substrate.
As semiconductor memory devices become highly integrated, a length of a gate electrode of a transistor included in the semiconductor memory device may be decreased rapidly. As the length of the gate electrode may be reduced, problems, e.g., short channel effects, arise in the transistor. Substantially, the short channel effect may be a common name for several problems generated in a transistor, and may include typical problems, e.g., an increase in a leakage current, a decrease in a breakdown voltage, and a continuous increase of a current due to a drain voltage.
Recently, as degrees of integration of a semiconductor memory device become a giga bite, a development of a transistor having a design rule below a current exposure threshold value may be newly required. As a result, a transistor having a horizontal channel region defined by the source and drain regions in the same plane may have difficulties in application to a currently highly integrated semiconductor memory device. Accordingly, a transistor having a vertical channel region defined by source and drain regions formed in a vertical direction with respect to a substrate has been developed. The transistor having a vertical channel region may include a lower active structure provided on a substrate, an upper active structure provided on the lower active structure, an gate insulation layer surrounding the upper active structure, a gate electrode formed on the gate insulation layer and impurity regions formed on upper and lower portions of the gate electrode.
The impurity regions of the vertical channel transistor may be electrically connected to a wiring or a capacitor. Generally, the wiring or the capacitor may be electrically connected to the impurity regions through a contact. Because the contact connects the wiring or the capacitor to the impurity regions, the contact may be required to have a relatively low resistance. Accordingly, the contact may be formed mainly using metal. However, during a sequential process, as metal atoms included in the contact may be diffused to the impurity region, the resistance of the contact may be increased. To prevent or reduce diffusions of the metal atoms from the contact to the impurity regions, a contact formed using polysilicon doped with impurities may be used. However, as the degrees of integration of a semiconductor memory device may be increased greatly, the contact area between the impurity region and the contact may be decreased. As a result, a problem that the contact resistance between the contact and the impurity region is increased may occur.